With recent development in technology for miniaturizing semiconductor devices and accelerating the processing speed thereof, the amount of data communicated between devices or LSIs (Large Scale Integrations) provided in the devices is increasing more than ever. With increasing amount of communicated data, it is desirable that the number of terminals (pads) required for data communications also increase. Nevertheless, a strict restriction is still posed on the number of terminals in an LSI, which affects the costs. For the purpose of achieving high-speed data communications with a fewer number of terminals in an LSI, the interface standards employing serial transmission have widely prevailed.
In the serial transmission scheme, it is common to superimpose information regarding clock edges onto serial data. It is therefore necessary to limit a run-length indicated by the number of consecutive bits each having a value of either “0” or “1”. In this scheme, it is also desirable that transmission be performed with good DC balance, i.e. frequency of values “0” and “1” within a predetermined time period. In order to limit the run-length and maintain the DC balance, channel coding is used in the serial transmission.
One example of the channel coding is symbol mapping in which an m-bit data character is mapped to an n-bit (m<n) encoded symbol. Another example of the channel coding is scrambling in which a bit pattern of a data character of consecutive m bits is randomized to generate an encoded block.
Patent Literature 1 discloses 8B/10B coding as an example of the symbol mapping. Non-Patent Literature 1 discloses 64B/66B coding as an example of the scrambling.
Patent Literature 2 discloses technology for switching between the symbol mapping and the scrambling after error detection/correction bits are added using the scrambling so that a word length in coding in the scrambling matches that in the symbol mapping.